The present invention relates to interconnection and routing techniques for integrated circuit components, and more particularly, but not exclusively relates to a multilevel architecture having greater layout flexibility that facilitates higher routing and interconnection density.
The need for faster and more complex electronic components fuels a desire to decrease the size of integrated circuit components. Correspondingly, it is often desirable to reduce the size of electrical interconnects for these components while maintaining high reliability and low electrical resistance. Highly conductive materials, such as metals, are often necessary for forming integrated circuit interconnects. One approach is to form a stack of interconnected layers that each include a pattern of elongate metal traces or via plugs insulated from one another by a dielectric. Usually, vertical via plugs in one layer are used to provide electrical connection between adjacent layers. Photolithographic patterning and associated etching processes typically provide the desired pattern for each layer. Unfortunately, the current desire to shrink the critical dimensions of active integrated circuit transistors deep into the submicron range (e.g. less than about 0.25 microns) limits the ability to correspondingly reduce metal conductor size through direct metal etching. As a result, new approaches have been sought to provide for the corresponding increased density of integrated circuit device interconnections.
FIG. 1 illustrates further limitations of existing approaches. Integrated circuit 50 of FIG. 1 includes substrate 52 with component connection sites 56a, 56b therealong. Oxide layer 60 covers substrate 52 and defines via holes for metal via plugs 62a, 62b to electrically contact sites 56a, 56b, respectively. Layer 64 is formed on top of layer 60 to provide a pattern of metal traces 66 insulated from each other by a dielectric--typically a silica (silicon dioxide) based material. Two of traces 66 are shown in electrical contact with plugs 62a, 62b to provide selected electrical contact with sites 56a, 56b, respectively.
Layer 70 is formed on layer 64 and includes a pattern of metallic via plugs 72 insulated from each other by a dielectric--also usually a silica-based material. Layer 74 is formed on layer 70 and includes a pattern of metal traces 76 insulated from each other in a similar manner to layer 64. Plugs 72 of layer 70 interconnect selected traces 66 and 76 of layers 64 and 74, respectively, to provide a predetermined wiring pattern for circuit 50. It should be noted that traces 66 include a crossunder connection specifically designated by reference numeral 66a to provide electrical coupling between two traces 76 of layer 74 that are separated by another trace specifically designated by reference numeral 76b. Similarly, traces 76 include a crossover connection designated by reference numeral 76a to provide electrical coupling between two traces 66 of layer 64. Notably, crossover 76a is routed around the trace specifically designated by reference numeral 66b by elevation to the next metallization level of layer 74. The crossover and crossunder connections have a longitudinal orientation that is generally perpendicular to the longitudinal orientation of other traces contained in the same layer. This orientation tends to limit the number of traces that may be included in a given layer.
A similar limitation to the "packing density" of integrated circuit interconnects arises from the occupation of layer "real estate" by dedicated, long-distance power supply bus traces in the same layer as long-distance signal carrying traces. Typically, power supply traces are about 10 to 50 times wider than other types of signal routings. Also, the more costly dielectric materials often utilized to preserve the integrity of long-distance, time-varying signal conductors are usually not needed for power supply conductors. Traces designated by reference numerals 66b, 76b in layers 64, 74, are representative of power supply bus connections of existing integrated circuit arrangements.
Thus, a need remains for techniques to further increase the density of integrated circuit component interconnects. The present invention satisfies this need, generally improves integrated circuit layout flexibility, and provides other significant benefits and advantages.